1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device capable of electrically overwriting data, and in particular to a nonvolatile semiconductor memory device capable of writing data at a high speed and a writing method thereto.
2. Description of the Related Art
In recent years, a nonvolatile semiconductor memory device, in particular a flash memory has been used in a variety of applications because it is capable of electrically overwriting data and retains data even when the power is turned OFF. For example, a flash memory is used as a storage for storing data in a portable terminal such as a cell phone, a digital camera, or a silicon audio player. The flash memory is mounted as storage for storing programs on a system LSI of a microcomputer. This reduces the development period of a device where the flash memory is set.
Data write time of a flash memory is relatively long, on the order of microseconds. Typically, a plurality of data items are previously stored into a latch circuit and then the plurality of data items stored in the latch circuit are written as a single unit, thereby reducing the effective write time.
The write operation of a related art flash memory (a nonvolatile semiconductor memory device) is described below referring to FIGS. 13 through 16 (for example, refer to Unexamined Japanese Patent Publication No. Hei-7-226097 or Unexamined Japanese Patent Publication No. Hei-11-328981.
FIG. 13 shows the configuration of the memory cell array and write circuit of a related art flash memory (a nonvolatile semiconductor memory device). In FIG. 13, the memory cell array 1 is a NOR-type flash memory cell array. To be more specific, the memory cell array 1 comprises word lines WL1, WL2 (only two word lines are shown) and bit lines BL1 through BLN. At the intersections of word lines and bit lines are arranged memory cells M11 through M2N in a matrix shape. A control gate for the memory cells is connected to the word lines WL1, WL2, a drain to bit lines BL1, BL2, a source a source line SL, and a substrate to a well line PW. The source for the memory cells M11 through M2N is connected to a common source line SL and the substrate to a common well line PW to form a single erase block.
Bit line reset circuits are respectively connected to the bit lines BL1 through BLN. The bit line reset circuit connected to the bit line BL1 is described below. The bit line reset circuit consists of a bit line reset transistor RT1. The bit line reset transistor RT1 has a gate connected to a bit line reset control signal BLRST, a source connected to a ground potential, and a drain connected to a bit line BL1. The bit line reset transistor RT1 plays a role of setting the bit line BL1 to the ground potential by way of the bit line reset control signal BLRST. The same circuit is connected to each of the bit line reset circuits connected to the bit lines BL2 through BLN.
Write circuits 2-1 through 2-N are respectively connected to the bit lines BL1 through BLN. A write circuits is arranged for each bit line, so that it is possible to perform batch write operation to all memory cells connected to a single word line with single write operation. For example, N memory cells M11 through M1N connected to the word line WL1 comprises Page 1, and selecting the word line WL1 in write operation performs batch write to Page 1. Similarly, N memory cells M21 through M2N connected to the word line WL2 comprises Page 2, and selecting the word line WL2 in write operation performs batch write to Page 2.
Next, the configuration of write circuits 2-1 through 2-N connected to all bit lines is described taking as an example the write circuit 2-1 connected to the bit line BL1.
The write circuit 2-1 comprises a latch circuit LAT including inverters INV1 and INV2, a transfer gate TG including an N-channel transistor TGN and a P-channel transistor TGP, and a latch data storage switch TN including a N-channel transistor.
The latch circuit LAT is a circuit which temporarily latches write data. To the power supply for the inverters INV1 and INV2 is supplied the output voltage VPP of a positive high voltage generating circuit (not shown in FIG. 13).
The transfer gate TG is a switch for connecting or interrupting the output N1 of the latch circuit LAT and the bit line BL1 and is controlled by a transfer gate control signal TGS. The transfer gate control signal TGS is connected to the gate of the N-channel transistor TGN. The output signal of the inverter ILS to which the transfer gate control signal TGS is input is connected to the gate of the P-channel transistor TGP. To the power supply for the inverter ILS and the substrate of the P-channel transistor TGP is supplied a high voltage VPP.
The latch data storage switch TN is a switch for connecting or interrupting external input data IO and the input N2 of the latch circuit LAT. The output signal of an AND logical element AND to which a data latch control signal DL and a latch selection signal LATSEL are input is connected to the gate of the latch data storage switch TN. When write data is stored into a predetermined latch circuit, both the data latch control signal DL and the latch selection signal LATSEL are driven HIGH to open the latch data storage switch TN thereby setting external input data IO to the latch circuit LAT.
When program data (0 data) is stored, the output N1 of the latch circuit LAT is set to HIGH. When erase data (1 data) is stored, the output N1 of the latch circuit LAT is set to LOW. After the data is stored, the latch data storage switch TN closes to retain write data in the latch circuit LAT.
While the configuration of the write circuit connected to the bit line BL1 has been described, same circuits are connected to the write circuits 2-2 through 2-N connected to the bit lines BL2 through BLN.
Write operation of the write circuit thus configured is described below.
FIG. 14 is a flowchart explaining the write operation of a related art flash memory (nonvolatile semiconductor memory device). The flowchart shows a case where write operation is performed to the memory cell for Page 1 connected to the word line WL1 and the memory cell for Page 2 connected to the word line WL2.
First, input of a program command starts the write operation (step S100). To perform Page 1 write operation (Page Program1), Page 1 write data is stored into the latch circuit LAT (step S110) After data latch is complete, Page 1 program operation is performed (step S120).
After the program operation is over, verify operation is performed to check that data has been properly written into the memory cell for Page 1 (step S130). In case it is determined that there is a memory cell where data, even single-bit data, is not properly written in the verify operation (this case is hereinafter called fail), program operation and verify operation are performed again (step S140). A plurality of program operations and verify operations are performed and in case it is determined that all memory cells on Page 1 have been properly written (this case is hereinafter called pass), Page 1 write operation is complete, followed by Page 2 write operation (Page Program2).
Same as Page 1 write operation, Page 2 write operation is performed by data latch operation (step S150), program operation (step S160), verify operation (step S170), and repetition of program operation and verify operation until verify operation has been passed (step S180). A plurality of program operations and verify operations are performed and in case verify operation has been passed, Page 2 write operation is complete and Page 1 and Page 2 write operations are terminated (step S190).
FIG. 15 is a timing chart explaining the write operation of a related art flash memory (nonvolatile semiconductor memory device). The timing chart shows the operation waveforms of a data latch control signal DL, the output voltage VPP of a positive high voltage generating circuit (not shown in FIG. 13), the output voltage VNN of a negative high voltage generating circuit (not shown in FIG. 13), and word lines WL1, W2.
In Page 1 write operation (Page Program1), in the first place, data latch to the latch circuit LAT is performed by way of the data latch control signal DL (Data Latch1). In the data latch period, the word lines WL1, WL2, the source line SL, and the well line PW are set to the ground potential. The transfer gate TG is in the inactive state while the bit line reset circuit is in the active state and the bit line is set to the ground potential.
After data latch is over, the system makes a transition to the program mode. The positive high voltage generating circuit and the negative high voltage generating circuit respectively generate high voltages of 5 V (VPP) and −8 V (VNN) necessary for program operation. Once the output voltages VPP, VNN of the positive high voltage generating circuit and the negative high voltage generating circuit have reached predetermined voltages, the word line WL1 is set to −8 V, the source line SL is placed in the high impedance state, the bit line reset circuit in the inactive state, and the transfer gate TG in the active state, then the output N1 of the latch circuit LAT is connected to the bit lines. This starts program operation.
In case program data (0 data) is stored in the latch circuit LAT, the output N1 of the latch circuit LAT is set to HIGH so that a positive high voltage of 5 V is applied to the bit lines. In case erase data (1 data) is stored in the latch circuit LAT, the output N1 of the latch circuit LAT is set to LOW so that a ground potential (0 v) is applied to the bit lines.
A voltage of −8 V is applied to the control gate (word lines) for the memory cell. When a voltage of 5 V is applied to the drain (bit lines), a high electric field is applied to the tunnel oxide film and electrons accumulated at the floating gate by way of an FN (Foeler-Nordheim) current is drawn toward the drain, which executes the program. When a ground voltage (0 V) is applied to the drain (bit lines), a high electric field to generate an FN current on the tunnel oxide film is not applied so that the memory cell program is not executed. After the program is executed for a predetermined period, the word line WL1 and the source line SL are set to a ground potential, the transfer gate TG is placed in the inactive state and the bit line reset circuit in the active state, then the bit lines are set to a ground potential. This completes program operation and makes a transition to the verify mode.
After the system has made a transition to the verify mode, the positive high voltage generating circuit and the negative high voltage generating circuit respectively generate a power supply voltage VDD and the voltage of a ground potential VSS, After the output voltages VPP, VNN of the positive high voltage generating circuit and the negative high voltage generating circuit have reached predetermined voltages, the bit line reset circuit is placed in the inactive state and the transfer gate TG in the active state to pre-charge only bit lines corresponding to program data (output N1 of the latch circuit LAT is HIGH) to the power supply voltage VDD.
After pre-charging of the bit lines is over, the transfer gate TG is placed in the inactive state, and the latch circuit is isolated from the bit lines and a voltage of 1 V is applied to the word line WL1.
In case the threshold voltage of the memory cells is less than 1 V, that is, in case the memory cells are properly programmed, the bit lines are discharged via the memory cells and the potential of the bit lines decreases toward the ground potential. In case the threshold voltage of the memory cells is 1 V or more, that is, in case the memory cells are not properly programmed, the bit lines are not discharged via the memory cells and the potential of the bit lines is maintained at the power supply voltage VDD.
After a predetermined period has elapsed, the transfer gate TG is placed in the active state and the latch circuit LAT is connected to the bit lines. In case the threshold voltage of the memory cells is less than 1 V, that is, in case the memory cells are properly programmed, the output N1 of the latch circuit LAT is driven LOW (erase data) because the bit lines are discharged to the ground potential, and the subsequent program is not executed. In case the threshold voltage of the memory cells is 1 V or more, that is, in case the memory cells are not properly programmed, the output N1 of the latch circuit LAT is maintained at the first set data, and the program is executed again in the subsequent program operation.
After a predetermined period has elapsed, verify operation is terminated by setting the word line W1 to the ground potential, placing the transfer gate TG in the inactive state and the bit line reset circuit in the active state to set the bit lines to the ground potential. In case it is determined that there remains program data, even single-bit data (fail), program operation (Program1) and verify operation (Verify1) are performed again.
In case the latch data in all latch circuits have been overwritten with erase data by a plurality of program operations and verify operations (pass), Page 1 write operation is complete. Then Page 2 write operation (Page Program 2) on WL2 is performed. Same as Page 1 write operation, Page 2 write operation is performed by repetition of data latch operation (Data Latch2), program operation (Program2) and verify operation (Verify2).
FIG. 16 shows the write command and the internal operation state of a related art flash memory (nonvolatile semiconductor memory device). In the first place, a program command CM1 and a program address AD1 on Page 1 are input. Then Page 1 write data is input. Inputting a program command CM2 after write data has been input provides the busy state, which starts Page 1 write operation. The write operation is executed by repeating program operation and verify operation. In case verify operation has been passed, Page 1 write operation is complete. After Page 1 write operation is complete, the system enters the ready state, allowing Page 2 write operation.
Next, the program command CM1 and a program address AD2 on Page 2 are input. Then Page 2 write data is input. Inputting a program command CM2 after write data has been input provides the busy state, which starts Page 2 write operation. Same as Page 1, Page 2 write operation is executed by repeating program operation and verify operation. In case verify operation has been passed, Page 2 write operation is complete.
The aforementioned related art nonvolatile semiconductor memory device (flash memory) has the following problems. Firstly, data latch time to store write data into a latch circuit is required. In recent years, the storage capacity of a nonvolatile semiconductor memory device has been growing. By increasing the number of bits (number of batch write bits) per page, the effective write time has been reduced. However, with an increase in the number of write bits per page, the data latch time in data write to a single page increases thus increasing the write time. A nonvolatile semiconductor memory device in recent years may require a long data latch time per page on the order of microseconds, which has significant effects on the increase in the write time.
Secondly, program operation and verify operation are repeated in the write operation to a page. Thus the high voltage generating circuit must generate a voltage required for program operation or verify operation each time program operation or verify operation takes place. This means that time until the predetermined voltage output from the high voltage generating circuit is stabilized, that is, the voltage output stabilization wait time is needed before starting verify operation. For example, referring to FIG. 15, it is necessary to wait as long as the time Tps before the output voltages VPP, VNN of the high voltage generating circuit are stabilized in program operation. It is also necessary to wait as long as the time Tpvs before the output voltages VPP, VNN of the high voltage generating circuit are stabilized in verify operation. The voltage output stabilization wait time is on the order of microseconds, which increases the write time. The increase in the storage capacity of a nonvolatile semiconductor memory device increases the number of cycles of program operation and verify operation and the voltage output stabilization wait time has great effects on the increase in the write time.
Thirdly, program operation and verify operation are repeated in the write operation to a single page. It is thus necessary to apply a program voltage or verify voltage on word lines each time program operation or verify operation takes place. As a result, the word line voltage rise time and fall time are required for each of program operation and verify operation. For example, in FIG. 15, the fall time Tp1 is required to apply a voltage of −8 V to the word lines at the start of program operation. The rise time Tp2 is required to drive the word lines to the ground potential at the end of program operation. The rise time Tpv1 is required to apply a voltage of −1 V to the word lines at the start of verify operation. The fall time Tpv2 is required to drive the word lines to the ground potential at the end of verify operation. The increase in the storage capacity of a nonvolatile semiconductor memory device increases the number of cycles of program operation and verify operation and the word line rise time and fall time have great effects on the increase in the write time.